1. Field of the Invention
This invention relates to data processing systems and more particularly to apparatus for testing and verifying the timing and logic of a cathode ray tube display subsystem.
2. Description of the Prior Art
Cathode ray tube (CRT) displays are used in current-day data processing systems as a terminal for accessing or updating a data base stored in a memory. Information from the data base is displayed on the face of the CRT in the form of characters made up of a dot matrix. Typically such dot matrices are 7 dots wide by 9 dots high in an area which is the equivalent of 9 dots wide by 12 dots high.
In a raster scan CRT display, an electron beam starts in the upper lefthand corner of the CRT, moves horizontally across the screen and returns. This action is called a horizontal scan. After each horizontal scan, the beam is incrementally moved down in the vertical direction until it reaches the bottom of the CRT. The beam is then moved vertically to its starting position.
As the beam progresses horizontally across the face of the tube, narrow voltage pulses are applied to the beam which show up as light spots on the face of the tube. Therefore 9 horizontal scans of the beam would display a row of characters. Three horizontal scans separate adjacent rows.
Therefore, 300 horizontal scans will display 25 rows of characters (12.times.25=300). However, there may be typically 317 scan lines. Each scan line takes 52.569 microseconds. The total sweep time for the 317 scan lines is 16.66 milliseconds (52.569.times.317) or at a 60 hertz rate.
A character generator typically applies signals in parallel to a shift register. The parallel signals represent the dot pattern for one horizontal scan line for one character position on the face of the CRT. The signals are shifted into the horizontal sweep logic in synchronization with the electron beam and a dot is displayed for each signal.
There are a number of difficulties in maintaining installed CRT displays. The character generator, shift register and other related components are difficult to debug as a system by normal read/write means because of the fast timing circuitry; typically a 16.9 megahertz signal provides the timing. Also an incorrect horizontal sweep frequency may damage the horizontal oscillator in the horizontal video circuit.